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DOI: 10.4230/OASIcs.WCET.2006.672

PLRU Cache Domino Effects

Authors: Christoph Berg

Published in: OASIcs, Volume 4, 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06) (2006)

Abstract

Domino effects have been shown to hinder a tight prediction of worst case execution times (WCET) on real-time hardware. First investigated by Lundqvist and StenstrÃƒÂ¶m, domino effects caused by pipeline stalls were shows to exist in the PowerPC by Schneider. This paper extends the list of causes of domino effects by showing that the pseudo LRU (PLRU) cache replacement policy can cause unbounded effects on the WCET. PLRU is used in the PowerPC PPC755, which is widely used in embedded systems, and some x86 models.

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Christoph Berg. PLRU Cache Domino Effects. In 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06). Open Access Series in Informatics (OASIcs), Volume 4, pp. 1-3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{berg:OASIcs.WCET.2006.672,
  author =	{Berg, Christoph},
  title =	{{PLRU Cache Domino Effects}},
  booktitle =	{6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)},
  pages =	{1--3},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-03-3},
  ISSN =	{2190-6807},
  year =	{2006},
  volume =	{4},
  editor =	{Mueller, Frank},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2006.672},
  URN =		{urn:nbn:de:0030-drops-6723},
  doi =		{10.4230/OASIcs.WCET.2006.672},
  annote =	{Keywords: Embedded systems, predictability, cache memory, PLRU, domino effects, timing anomalies}
}

Document

DOI: 10.4230/DagSemProc.03471.4

Requirements for and Design of a Processor with Predictable Timing

Authors: Christoph Berg, Jakob Engblom, and Reinhard Wilhelm

Published in: Dagstuhl Seminar Proceedings, Volume 3471, Perspectives Workshop: Design of Systems with Predictable Behaviour (2004)

Abstract

This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design of a hard real-time processor with predictable timing, which is simultaneously capable of reaching respectable performance levels. The design principles we identify are recoverability from information loss in the analysis, minimal variation of the instruction timing, non-interference between processor components, deterministic processor behavior, and comprehensive documentation. The principles are based on our experience and that of other researchers in building timing analysis tools for existing processors.

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Christoph Berg, Jakob Engblom, and Reinhard Wilhelm. Requirements for and Design of a Processor with Predictable Timing. In Perspectives Workshop: Design of Systems with Predictable Behaviour. Dagstuhl Seminar Proceedings, Volume 3471, pp. 1-20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2004)

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@InProceedings{berg_et_al:DagSemProc.03471.4,
  author =	{Berg, Christoph and Engblom, Jakob and Wilhelm, Reinhard},
  title =	{{Requirements for and Design of a Processor with Predictable Timing}},
  booktitle =	{Perspectives Workshop: Design of Systems with Predictable Behaviour},
  pages =	{1--20},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2004},
  volume =	{3471},
  editor =	{Lothar Thiele and Reinhard Wilhelm},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/DagSemProc.03471.4},
  URN =		{urn:nbn:de:0030-drops-57},
  doi =		{10.4230/DagSemProc.03471.4},
  annote =	{Keywords: WCET, hard real-time, embedded systems, computer architecture}
}

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Documents authored by Berg, Christoph

PLRU Cache Domino Effects

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Requirements for and Design of a Processor with Predictable Timing

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